Espressif Systems /ESP32-P4 /AHB_DMA /OUT_CONF0_CH0

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as OUT_CONF0_CH0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OUT_RST_CH0)OUT_RST_CH0 0 (OUT_LOOP_TEST_CH0)OUT_LOOP_TEST_CH0 0 (OUT_AUTO_WRBACK_CH0)OUT_AUTO_WRBACK_CH0 0 (OUT_EOF_MODE_CH0)OUT_EOF_MODE_CH0 0 (OUTDSCR_BURST_EN_CH0)OUTDSCR_BURST_EN_CH0 0 (OUT_DATA_BURST_EN_CH0)OUT_DATA_BURST_EN_CH0 0 (OUT_ETM_EN_CH0)OUT_ETM_EN_CH0

Description

Configure 0 register of Tx channel 0

Fields

OUT_RST_CH0

This bit is used to reset AHB_DMA channel 0 Tx FSM and Tx FIFO pointer.

OUT_LOOP_TEST_CH0

reserved

OUT_AUTO_WRBACK_CH0

Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.

OUT_EOF_MODE_CH0

EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in AHB_DMA

OUTDSCR_BURST_EN_CH0

Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.

OUT_DATA_BURST_EN_CH0

Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.

OUT_ETM_EN_CH0

Set this bit to 1 to enable etm control mode, dma Tx channel 0 is triggered by etm task.

Links

() ()